1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated integrated circuits, and, more particularly, manufacturing methods for back side processing of through-silicon vias (TSV's) and the resulting interconnect structures.
2. Description of the Related Art
In recent years, the device features of modern, ultra-high density integrated circuits have been steadily decreasing in size in an effort to enhance the overall speed, performance, and functionality of the circuit. As a result, the semiconductor industry has experience tremendous growth due to the significant and ongoing improvements in integration density of a variety of electronic components, such as transistors, capacitors, diodes, and the like. These improvements have primarily come about due to a persistent and successful effort to reduce the critical dimension—i.e., minimum feature size—of components, directly resulting in the ability of process designers to integrate more and more components into a given area of a semiconductor chip.
Improvements in integrated circuit design have been essentially two-dimensional (2D)—that is, the improvements have been related primarily to the layout of the circuit on the surface of a semiconductor chip. However, as device features are being aggressively scaled, and more semiconductor components are being fit onto the surface of a single chip, the required number of electrical interconnects necessary for circuit functionality dramatically increases, resulting in an overall circuit layout that is increasingly becoming more complex and more densely packed. Furthermore, even though improvements in photolithography processes have yielded significant increases in the integration densities of 2D circuit designs, simple reduction in feature size is rapidly approaching the limit of what can presently be achieved in only two dimensions.
As the number of electronic devices on single chip rapidly increases, three-dimensional (3D) integrated circuit layouts, or stacked chip design, have been utilized for some semiconductor devices in an effort to overcome some of the feature size and density limitations associated with 2D layouts. Typically, in a 3D integrated circuit design, two or more semiconductor chips are bonded together, and electrical connections are formed between each chip. One method of facilitating the chip-to-chip electrical connections is by use of so-called through-silicon vias, or TSV's. A TSV is a vertical electrical connection element that passes completely through a silicon wafer or die, allowing for more simplified interconnection of vertically aligned electronic devices, thereby significantly reducing integrated circuit layout complexity, as well as the overall dimensions of a multi-chip circuit. Some of the benefits associated with the interconnect technology enabled by 3D integrated circuit designs include accelerated data exchange, reduced power consumption, and much higher input/output voltage densities.
Currently, most integration development has tended to focus on forming TSV's within an active area of the semiconductor die—e.g., via-middle and via-last schemes. However, irrespective of the integration scheme utilized, in most state-of-the-art TSV processing, through-silicon vias are typically formed in a wafer from the front side. The back side of the wafer is then processed so as to expose the TSV's, and interconnect structures are formed to facilitate electrical connections to another semiconductor chip during a chip packaging operation. A typical prior art process for the back side processing of TSV's is illustrated in FIGS. 1a-1g, and will now be described in detail below.
FIG. 1a is a schematic cross-sectional view depicting an early stage of a back side TSV processing operation in accordance with an illustrative prior art process. As shown in FIG. 1a, a semiconductor chip or wafer 100 is in a “flipped” position—i.e., with a back side 100b oriented up for the back side processing operations, and a front side 100f oriented down. The wafer 100 may comprise a substrate 101, which may represent any appropriate carrier material, such as silicon or silicon-based materials, and the like. Additionally, the wafer 100 may include a semiconductor layer 102 that may be made up of active areas (not shown) in which a plurality of schematically depicted active and/or passive circuit elements 103, such as transistors, capacitors, resistors and the like may be formed, in which case the semiconductor layer 102 may also be referred to as a device layer 102. Depending on the overall design strategy employed for the wafer 100, the substrate 101 may in some cases be a substantially crystalline substrate material (i.e., bulk silicon), whereas in other instances the 10substrate 101 may be formed on the basis of a silicon-on-insulator (SOI) architecture, in which a buried insulating layer (not shown) may be provided between the device layer 102 and the substrate 101. It should be appreciated that the semiconductor/device layer 102, even if comprising a substantially silicon-based material layer, may include other semiconducting materials, such as germanium, carbon and the like, in addition to appropriate dopant species for establishing the requisite active region conductivity type for the circuit elements 103.
The wafer 100 shown in FIG. 1a also illustrates a contact structure layer 104, which may be formed between the device layer 102 and a metallization system 105, where various conductive lines and contact vias (not shown) are formed to define a circuit layout, so as to provide electrical interconnects between the circuit elements 103 and the metallization system 105. The typical processing steps and materials used to form the circuit elements 103 in the device layer 102, the contact layer 104, and the metallization system 105 are well known in the art, and will not be further discussed.
The illustrative wafer 100 of FIG. 1a may also include one or more through-silicon vias (TSV's) 106 for facilitating electrical connections between two or more stacked chips, as previously described. Typically, during initial processing of the wafer 100 from the front side 100f, the TSV's 106 are only formed a partial distance through the substrate 101, such that the TSV's 106 extend to a depth 106d, and come to within a distance 106e of the back side 100b. For example, depending on the various processing parameters, such as the depth 106d, the material of the substrate 101, the width 106w of the TSV's 106, and the like, the sidewalls of the TSV's 106 may be slightly tapered, as shown in FIG. 1a, or they may be substantially vertical with respect to the front and back sides 100f, 100b. In some cases, the TSV's 106 may typically be made up of a suitable conductive material, such as copper or copper-based alloys, and may have an average width 106w ranging between approximately 1 μm and 10 μm. In some typical devices, the depth 106d of the TSV's 106 may range from approximately 40-60 μm, although in other devices the depth 106d may be less than 40 μm or greater than 60 μm, depending on the overall device design and processing parameters. Furthermore, and in some cases depending on the overall type of back side integration, the distance 106e may range between approximately 1 μm and 20 μm after the completion of an initial back side thinning or grinding operation.
A liner 107 may be positioned between the TSV 106 and the substrate 101 so as to electrically isolate the TSV 106, and in some cases, to substantially prevent the material of the TSV 106 from diffusing into the substrate 101, a situation which could create undesirable conducting paths in the circuit, and potentially lead to a commensurate degradation in overall device performance. The material of the liner 107 may have a thickness in the range of 100-200 nm, and may be made up any suitable insulating dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, and the like. Additionally, in some cases a diffusion barrier layer (not shown) may be formed between the liner 107 and the TSV's 106 so as to prevent the material of the TSV's 106 for diffusing into and/or through the liner 107 and into the substrate 101, the device layer 102, or the contact structure layer 104.
As shown in FIG. 1a, during back side TSV processing, the wafer 100 may be exposed to an initial etch back process 121 that is adapted to selectively remove a portion 101t of the substrate 101 in preparation for exposing the copper or copper alloy material of the TSV's 106. For example, in some instances, the etch back process 121 may be an appropriately designed isotropic wet or dry etch process, based on a recipe that selectively removes a silicon-containing semiconductor material of the substrate 101 relative to a silicon dioxide material of the liner 107, such as a combination of hydrofluoric (HF) and nitric (HNO3) acids and the like. Other recipes well known in the art may also be used.
FIG. 1b shows the illustrative wafer 100 after completion of the etch back process 121, and where the portion 101t of the substrate 101 has been etched away. Thereafter, a deposition process 122 may be performed so as to form a dielectric protection layer 108 above the exposed surfaces of the back side 100b of the wafer 100, so as to protect the material of the substrate 101 during subsequent processing steps, as will be described more fully below. Depending on the overall device processing requirements, the dielectric protection layer 108 may be any suitable dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, silicon carbonitride, and the like.
As shown in FIG. 1c, the wafer 100 may then be subjected to planarization process 123, which may be, for example, a chemical mechanical polishing (CMP) process and the like, so as to planarize the back side 100b of the wafer 100, and to expose a surface 106s of the material of the TSV's 106 for further processing. Due to the various different types of materials that may be encountered during the planarization, or CMP, process 123—i.e., the dielectric protection layer 108, the liner 107, and the TSV 106—the CMP process 123 may be designed to include multiple consecutive planarizing steps, where the CMP recipe used for each individual planarizing step may be appropriately tailored and/or adjusted to the specific combination of materials being planarized.
FIG. 1d schematically illustrates the wafer 100 of FIG. 1c after completion of the CMP process 123. As noted above, the dielectric protection layer 108 may serve to protect the back side 100b of the wafer 100 during the final stages of the CMP process 123. For example, depending on the specific processing parameter, the material that makes up the TSV's 106 may tend to smear across the planarized back side surface 100s of the wafer 100 during the CMP process 123. For example, in those instances where the TSV's are made up of copper and/or copper alloy materials and the substrate 101 is made up of silicon and/or silicon-based materials, the copper-based material of the TSV's 106 may contaminate, and diffuse into, the silicon-based material of the substrate 101. However, with the dielectric protection layer 108 present above the back side 100b of the wafer 100, any material of the TSV's 106 that smears during the CMP process 123 will remain on the surface 100s the presence of the dielectric protection layer 108 may serve to substantially prevent such contamination and/or diffusion from occurring, thereby potentially avoided the subsequent device degradation, as previously described. Accordingly, as shown in FIG. 1d, portions of the dielectric protection layer 108 may be left in place above the exposed areas of the substrate 101 throughout the CMP process 123, thereby protecting and isolating the substrate 101 during the CMP process 123, as well as during further processing steps, as described below.
Also as shown in FIG. 1d, a material deposition process 124 may be performed so as to form a conductive material layer 110 above the planarized back side surface 100s in preparation for forming contact structures, as is more fully described below. In some cases the conductive material layer 110 may be formed so as to be in electrical contact with the TSV's 106, although in some cases an intervening barrier and/or adhesion layer (not shown) may be formed between the conductive material layer 110 and the TSV's 106. Depending on the desired overall process flow, the conductive material layer 110 may be, for example, an aluminum-based metal layer, as may typically be used in some applications to form contact pads 110p (see, FIG. 1 e) for bump structures 112 (see, FIG. 1f).
FIG. 1e schematically depicts the illustrative wafer 100 of FIG. 1d during a further processing stage, after the aluminum-based conductive material layer 110 has been formed above the planarized back side surface 100s. As shown in FIG. 1e, a patterned etch mask layer 130, such as, for example, a patterned photoresist mask, may be formed above the conductive material layer 110. Thereafter, the back side 100b of the wafer 100 may be exposed to a suitably designed anisotropic etch process 125 so as to form contact pads 110p above portions of the dielectric protection layer 108 and each TSV 106 (see, FIG. 1f). The anisotropic etch process 125 may be adapted to selectively remove material of the conductive material layer 110 relative to the dielectric protection layer 108, recipes for which are well known in the art.
FIG. 1f schematically illustrates the wafer 100 of FIG. 1e in a subsequent processing stage, after the contact pads 110p have been formed, the patterned etch mask layer 130 has been removed, and a passivation layer 111 has been formed above the back side 100b of the wafer 100. As shown in FIG. 1f, the passivation layer 111 completely encloses each contact pad 110p, and furthermore extends above an upper surface 110s of each contact pad 110p, thereby substantially electrically isolating the respective contact pads 110p. Depending on the processing requirements, the passivation layer 111 may be a silicon-based dielectric material, such as silicon nitride, or an organic polymer material, such as a polyimide and the like. A second patterned etch mask 131 may then be formed above the passivation layer 111, and the back side 100b of the wafer 100 may be exposed to a suitable dry anisotropic etch process 126, such as a reactive ion etch (RIE) process and the like, so as to form openings 111a that expose a portion of the upper surfaces 110s of each contact pad 110p. 
FIG. 1g schematically illustrates the wafer 100 in a further advance manufacturing stage, after the second patterned etch mask 131 has been removed from above the passivation layer 111. Furthermore, completed interconnect structures 150 have been formed on the back side 100b of the wafer 100, which may be used to affect an electrical connection between the various stacked chips of a representative chip package. Each of the interconnect structures 150 may include, for example, a contact pad 110p that is in electrical contact with a TSV 106, and a bump structure 112 that has been formed in and above the openings 111a (see, FIG. 1f) so as to electrically contact the exposed portions of the upper surfaces 110s of the contact pads 110p. As shown in FIG. 1g, each bump structure 112 may include an underbump metallization (UBM) layer 112u and a solder ball 112b. The various processing steps used for forming the bump structures 112 shown in FIG. 1g are well known in the semiconductor processing arts, and are therefore not described herein.
As noted, the interconnect structures 150 may be used to facilitate making the electrical connections that are required between one semiconductor chip and another in a stacked or 3D chip configuration. However, the above described process may impose some limitations on the overall layout of a given chip, and consequently, on the 3D circuit designs. For example, aluminum-based metal contact pads 110p are typically only formed directly above a TSV 106, and as such the locations of the contact pads 110p will be dictated by the specific locations of the TSV's 106. However, the specific locations of the TSV's 106 may be dictated by other chip layout criteria that may not conform to the most desirable layout for the bump structures 112, which would typically be based on a substantially uniform spacing and layout. In such cases, redistribution layers (RDL) are used to “relocate” secondary bond pads to more desirable, uniformly spaced positions on the back side 100b of the wafer 100. For most applications utilizing aluminum-based contact pads 110p, RDL process integration commonly requires additional processing steps to form patterned metal lines and additional passivation and/or insulating layers, thus increasing the overall integration complexity and cost.
Accordingly, there is a need to implement new design strategies to address the manufacturing and performance issues associated with the prior art methods that have commonly been used for performing back side TSV processing. The present disclosure relates to methods and structures for avoiding, or at least reducing, the effects of one or more of the problems identified above.